1. Field of the Invention
This invention is generally related to the field of semiconductor devices, and, more particularly, to a bipolar transistor with geometry optimized for device performance and a method of making same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating efficiency and reduce the size of bipolar junction transistors and integrated circuit devices incorporating such transistors. This drive is fueled by demands for electronic devices that operate at increasingly greater speeds, consume less power, and an overall desire for more physically compact devices. Power bipolar transistors are employed in a variety of integrated circuit devices. For example, such power bipolar transistors may be employed in a typical ADSL line driver or in a subscriber line interface card (SLIC) which are in widespread use in the telecommunications industry. Such power bipolar devices may operate in high voltage environments, e.g., 80–150 volts.
As is well known in the art, power bipolar transistors are typically fabricated on a silicon-on-insulator (SOI) substrate. Such power bipolar transistors may occupy a significant portion of the silicon area within a typical ADSL line driver or a typical SLIC, e.g., approximately 40% of the total silicon area. FIG. 1 is a schematic plan view of various implant regions in an illustrative prior art power bipolar transistor 10. As shown therein, the power bipolar transistor 10 has a so-called multiple-stripe layout configuration. The power bipolar transistor 10 may be formed in an active layer of an SOI substrate. The transistor 10 is generally comprised of a collector region 16, a plurality of emitter regions 18, a plurality of extrinsic base regions 20, and an intrinsic base region 22. The intrinsic base region 22 is sometimes referred to as the base box. A trench isolation region 24 surrounds the bipolar transistor 10. The methods of forming such doped regions in the illustrative multiple stripe bipolar transistor are well known to those skilled in the art. Additionally, when the bipolar junction transistor 10 is completed, contacts will be formed to these various doped regions as is known in the art. The particular type of dopant materials, e.g., N-type or P-type, used to form the various doped regions shown in FIG. 1 will vary depending upon the type of device under construction, e.g., an NPN transistor or a PNP transistor. Of course, the precise dopant concentrations of the various doped regions may vary depending on the particular application.
As stated previously, there is a constant drive to reduce the size of such power bipolar junction transistor devices, while at the same time maintaining or enhancing the performance characteristics of such devices. Since multiple stripe power bipolar transistors may occupy approximately 40% of the silicon area of a typical SLIC, optimizing the performance of the power amplifier per unit of silicon area is one viable means for reducing die size. Accordingly, a desire and need exist for a layout geometry for a power bipolar transistor that can eliminate, solve or reduce one or more of the problems identified above. The layout of prior art bipolar junction transistors is also configured so as to avoid or reduce problems associated with current crowding which may result in localized hot spots within such a device. Such current crowding may limit the performance capability of the device and, in some cases, result in device failure. However, in avoiding current crowding problems, such prior art bipolar transistors consume a relatively large amount of silicon area.
The present invention is directed to various devices and methods that may solve, or at least reduce, some or all of the aforementioned problems.